1. Technical Field
The disclosure herein relates to a semiconductor integrated circuit, and more particularly, to an apparatus and a method for generating error detection codes.
2. Related Art
A configuration for implementing a data bus inversion function, that is, a data bus inversion (DBI) unit is used to prevent a problem, such as simultaneous switching noise or inter-symbol interference, that is caused as the number of current data bits in entire data bits, of which logic values are changed when compared to previous data bits, increases in data transmission.
When the number of data bits with changed logic values are greater than one half of the entire number of data bits, the data bus inversion unit enables DBI flags such that inverted data is transmitted instead of normal data to decrease the number of the data bits to be switched to less than one half of the number of the entire data bits.
In the case of a semiconductor circuit as processing speed increases, the probability of an error to occur in data transmission increases. One example of this is in a semiconductor memory device such as a DRAM. Accordingly, an error detection code generation circuit can be used to generate and transmit error detection codes separately from data so that a data reception side can determine whether an error occurs in received data.
Conventional error detection code generation circuits have adopted CRC (cyclic redundancy check) logic, such as CRC8, in which error detection codes of 8 bits are output from 64 bits.
In a semiconductor circuit having a conventional data bus inversion unit, the configuration of an apparatus for generating error detection codes will be described below.
Referring to FIG. 1, a conventional apparatus configured to generate error detection codes includes a data bus inversion unit 10, an error detection code generation unit 20, an inverter IV1, and a multiplexer 40.
The data bus inversion unit 10 is configured to receive 64-bit data through data lines (GIO<0:7>) and generate 8-bit DBI flags.
The inverter IV1 is configured to invert and output the 64-bit data.
The multiplexer 40 is configured to selectively output the 64-bit data or 64-bit data inverted by the inverter IV1, in response to the DBI flags.
The operations of the conventional apparatus for generating error detection codes will be described below.
The data bus inversion unit 10 receives the 64-bit data and checks the number of data bits of which logic values are changed in every 8 bits when compared to previous data bits.
When the number of data bits in the entire data bits, of which logic values are changed, is greater than one half of the entire data bits, the data bus inversion unit 10 outputs the DBI flags to a low level.
When the DBI flags have a low level, the multiplexer 40 selects and outputs the data inverted through the inverter IV1.
The error detection code generation unit 20 generates and outputs error detection codes (CRC<0:7>) for the 64-bit data output from the multiplexer 40 and the 8-bit DBI flags.
The error detection code generation unit 20 generates the error detection codes (CRC<0:7>) by XORing the entire 64-bit data and 8-bit DBI flags, that is, 72 bits, in accordance with a CRC (cyclic redundancy check) logic.
The error detection codes (CRC<0:7>) are output through an EDC (error detection code) pin to an external system, for example, a GPU (graphic processing unit).
In the semiconductor circuit having the above-described data bus inversion unit 10, the 8-bit DBI flags are required to generate the error detection codes.
Therefore, in a conventional circuit, since an operation process for the generation of the error detection codes can be implemented after implementing an operation process for the data bus inversion function, a problem can occur due to that the fact that the time for generating the error detection codes is extended. This can degrade the performance of a system such as a semiconductor memory device.